SPI boot...
Initializing....using SPD
Not enough bank(chip-select) for CS0+CS1 on controller 0, interleaving disabled!
Loading second stage boot loader .................................................................................................ddr self refresh double times(0xfe00_8114):0c300100ddr self refresh interval(0xfe00_8124):0c300100

U-Boot 2015.01.IAP8350.8351_v0.02_ddr_refresh_rate+SDKv1.9+geb3d4fc (May 15 2016 - 22:53:21)

CPU0:  T1023E, Version: 1.0, (0x85490010)
Core:  e5500, Version: 2.1, (0x80241021)
Single Source Clock Configuration
Clock Configuration:
       CPU0:1200 MHz, CPU1:1200 MHz,
       CCB:400  MHz,
       DDR:800  MHz (1600 MT/s data rate) (Asynchronous), IFC:100  MHz
       QE:200  MHz
       FMAN1: 600 MHz
       QMAN:  400 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 0810000c 00000000 00000000 00000000
       00000010: 4a800003 80008812 ec027000 21000000
       00000020: 00000000 00000000 00000000 0002c500
       00000030: 00000104 44020201 00000000 00000006
Board: T1023WLAN, boot from SPI
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHZ
I2C:   ready
SPI:   ready
DRAM:  Detected UDIMM Fixed DDR on board
Not enough bank(chip-select) for CS0+CS1 on controller 0, interleaving disabled!
1 GiB (DDR3, 32-bit, CL=11, ECC off)
L2:    256 KiB enabled
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 149 (0x95)
MMC:   FSL_SDHC: 0
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
*** Warning - bad CRC, using default environment

EEPROM: Invalid ID (ff ff ff ff)
PCIe1: Root Complex, x1 gen1, regs @ 0xfe240000
  01:00.0     - 168c:0046 - Network controller
PCIe1: Bus 00 - 01
PCIe2: Root Complex, x1 gen1, regs @ 0xfe250000
  03:00.0     - 168c:0046 - Network controller
PCIe2: Bus 02 - 03
PCIe3: Root Complex, x1 gen1, regs @ 0xfe260000
  05:00.0     - 168c:0050 - Network controller
PCIe3: Bus 04 - 05
In:    serial
Out:   serial
Err:   serial
Net:   SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
Fman1: Uploading microcode version 108.4.2
Phy 26 not found
PHY reset timed out
FM1@DTSEC4 [PRIME]
Error: FM1@DTSEC4 address not set.
, FM1@TGEC1
Error: FM1@TGEC1 address not set.

Hit any key to stop autoboot:  0
WARNING: adjusting available memory to 30000000
Wrong Image Format for bootm command
ERROR: can't get kernel image!
--> printenv
baudrate=115200
bdev=sda3
bootargs=root=/dev/ram rw console=ttyS0,115200
bootcmd=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr
bootdelay=10
bootfile=uImage
consoledev=ttyS0
ethact=FM1@DTSEC4
ethprime=FM1@DTSEC4
fdtaddr=0x00c00000
fdtfile=t1023wlan/t1023wlan.dtb
fman_ucode=3f4f1c90
hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1
loadaddr=0x1000000
netdev=eth0
nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr
ramdiskaddr=0x02000000
ramdiskfile=t1023wlan/ramdisk.uboot
rootpath=/opt/nfsroot
tftpflash=tftpboot $loadaddr $uboot && protect off $ubootaddr +$filesize && erase $ubootaddr +$filesize && cp.b $loadaddr $ubootaddr $filesize && protect on $ubootaddr +$filesize && cmp.b $loadaddr $ubootaddr $filesize
uboot=u-boot.bin
ubootaddr=0x00201000
usb1:dr_mode=host,phy_type=utmi

Environment size: 1187/8188 bytes
--> bdinfo
memstart    = 0x00000000
memsize     = 0x40000000
flashstart  = 0x00000000
flashsize   = 0x00000000
flashoffset = 0x00000000
sramstart   = 0x00000000
sramsize    = 0x00000000
immr_base   = 0xFE000000
bootflags   = 0x00000000
intfreq     =   1200 MHz
busfreq     =    400 MHz
addressing  = 36-bit
ethaddr     = (not set)
IP addr     = <NULL>
baudrate    = 115200 bps
relocaddr   = 0x3FEF0000
-->