top	$abc$3123$lut$not$aiger3122$1	$lut	A	in	\ctr [0]
top	$abc$3123$lut$not$aiger3122$1	$lut	Y	out	$abc$3123$auto$rtlil.cc:2609:MuxGate$1039

Why does the below techmap.v not replace the above WIDTH==1 lut?

module \$lut (A, Y);
   parameter WIDTH = 0;
   parameter LUT = 0;
   
   (* force_downto *)
   input [WIDTH-1:0] A;
   output            Y;
   
   generate
      if (WIDTH == 1) begin
         LUT_SIMPLE _TECHMAP_REPLACE_ (.LUT_INIT({{4{LUT[1]}},{4{LUT[0]}}}), .Q(Y), .S0(1'b0), .S1(1'b0), .S2(A[0]));
      end if (WIDTH == 2) begin
         LUT_SIMPLE _TECHMAP_REPLACE_ (.LUT_INIT({{2{LUT[3]}},{2{LUT[2]}},{2{LUT[1]}},{2{LUT[0]}}}), .Q(Y), .S0(1'b0), .S1(A[0]), .S2(A[1]));
      end else if (WIDTH == 3) begin
         LUT_SIMPLE _TECHMAP_REPLACE_ (.LUT_INIT(LUT), .Q(Y), .S0(A[0]), .S1(A[1]), .S2(A[2]));
      end else begin
         wire _TECHMAP_FAIL_ = 1;
      end
   endgenerate
endmodule